自定義上升沿檢測

class RisingEdgeDetector extends Module {val io = IO(new Bundle {val inSig = Input(Bool())val outSig = Output(Bool())val clock = Input(Clock())})// 定義 risingedge 函數def risingedge(x: Bool): Bool = x && !RegNext(x)// 使用 risingedge 函數檢測上升沿io.outSig := risingedge(io.inSig)// Chisel 會為 RegNext 自動生成一個寄存器來保存 inSig 的值// 并在下一個時鐘周期提供這個值
}

實現主程序

package helloimport chisel3.{Clock, _}
class RisingEdgeDetector extends Module {val io = IO(new Bundle {val inSig = Input(Bool())val outSig = Output(Bool())})// 定義 risingedge 函數def risingedge(x: Bool): Bool = x && !RegNext(x)// 使用 risingedge 函數檢測上升沿io.outSig := risingedge(io.inSig)// Chisel 會為 RegNext 自動生成一個寄存器來保存 inSig 的值// 并在下一個時鐘周期提供這個值
}class risingedge extends Module {val io = IO(new Bundle {val detectedRisingEdge  = Output(Bool()) // IO names will be the sameval someBoolSignal  = Input(Bool())  // (without 'io_' in prefix)})// 創建 RisingEdgeDetector 模塊的實例val detector = Module(new RisingEdgeDetector)// 連接輸入和輸出detector.io.inSig := io.someBoolSignal // 這里的 someBoolSignal 應該是你的設計中的一個 Bool 類型的信號io.detectedRisingEdge := detector.io.outSig // 這將是一個 Bool 類型的信號，表示上升沿的檢測結果
}
object risingedgeMain extends App {(new chisel3.stage.ChiselStage).emitVerilog(new risingedge(), Array("--target-dir", "generated"))
}

運行以上chisel，生成Verilog如下

module RisingEdgeDetector(input   clock,input   io_inSig,output  io_outSig
);reg  _T; // @[risingedge.scala 11:48]wire  _T_1 = ~_T; // @[risingedge.scala 11:40]assign io_outSig = io_inSig & _T_1; // @[risingedge.scala 14:13]always @(posedge clock) begin_T <= io_inSig;end
endmodulemodule risingedge(input   clock,input   reset,output  io_detectedRisingEdge,input   io_someBoolSignal
);wire  detector_clock; // @[risingedge.scala 26:24]wire  detector_io_inSig; // @[risingedge.scala 26:24]wire  detector_io_outSig; // @[risingedge.scala 26:24]RisingEdgeDetector detector ( // @[risingedge.scala 26:24].clock(detector_clock),.io_inSig(detector_io_inSig),.io_outSig(detector_io_outSig));assign io_detectedRisingEdge = detector_io_outSig; // @[risingedge.scala 29:25]assign detector_clock = clock;assign detector_io_inSig = io_someBoolSignal; // @[risingedge.scala 28:21]
endmodule