Exercise
For the 5-stage pipeline (RR and RW take half a cycle)
For the following pairs of instructions, how many stalls will the 2nd instruction experience (with and without bypassing)?
1.
ADD R3 ?R1+R2
ADD R5 ? R3+R4 ?
Answer:0 stall with bypassing,2 stalls without bypassing
No bypassing
F | D | E | M | W | |||||
F | S | S | D | E | M | W |
?bypassing
F | D | E | M | W | |||||
F | D | E | M | W |
2.
LD R2 ? [R1]
ADD R4 ? R2+R3
Answer:1 stall with bypassing,2 stalls without bypassing
No bypassing
F | D | E | M | W | |||||
F | D | S | S | E | M | W |
?bypassing
F | D | E | M | W | |||||
F | D | S | E | M | W |
R1所映射的存儲器的值在訪存后才知道是多少
3.
LD R2 ? [R1]
SD R3 ? [R2]
Answer:1 stall with bypassing,2 stalls without bypassing
No bypassing
F | D | E | M | W | |||||
F | D | S | S | E | M | W |
?bypassing
F | D | E | M | W | |||||
F | D | S | E | M | W |
- LD R2 ? [R1]
- 取指階段:從存儲器中讀取指令LD R2 ? [R1]
- 譯碼階段:譯碼指令,得到操作碼、寄存器地址和偏移量,從寄存器堆中讀取R1的值
- 執行階段:將R1的值加上偏移量,得到存儲器地址
- 訪存階段:從存儲器中讀取該地址的數據
- 寫回階段:將數據寫入R2寄存器
- SD R3 ? [R2]
- 取指階段:從存儲器中讀取指令SD R3 ? [R2]
- 譯碼階段:譯碼指令,得到操作碼、寄存器地址和偏移量,從寄存器堆中讀取R2和R3的值
- 執行階段:將R2的值加上偏移量,得到存儲器地址
- 訪存階段:將R3的值寫入存儲器中該地址的位置
- 寫回階段:無
4.
LD R2 ? [R1]
SD R2 ? [R3]
Answer:0 stall with bypassing,2 stalls without bypassing
No bypassing
F | D | E | M | W | |||||
F | D | S | S | E | M | W |
?bypassing
F | D | E | M | W | |||||
F | D | E | M | W |