1. Fsm1（Simple FSM 1 - asynchronous reset）

????????狀態機可分為兩類：

? ? ? ? （1）Mealy狀態機：輸出由當前狀態和輸入共同決定。輸入變化可能立即改變輸出。

? ? ? ? （2）Moore狀態機：輸出僅由當前狀態決定，與輸入無關。輸出更穩定，但可能對輸入響應較慢。

注意：本題是實現Moore狀態機，但其狀態轉移邏輯是由當前狀態與輸入共同決定的，該點容易混淆。

????????首先根據當前狀態值得出輸出

? ? ? ? ? ? ? ? out = (state == B);

然后根據Fsm1的狀態轉移圖判斷出其狀態轉移邏輯，該部分使用組合邏輯電路實現。狀態轉移表具體如表1所示：

表1? Fsm1的狀態轉移表

最后對當前狀態值進行更新賦值，該部分使用時序邏輯電路實現。

module top_module
#(parameter 	A = 0,parameter 	B = 1
)
(output	out,input 	clk,input 	areset,input 	in
);reg state;reg next_state;// 狀態值更新always @(posedge clk, posedge areset) beginif (areset == 1'b1) beginstate <= B;end else beginstate <= next_state;endend// 狀態值轉換always @(*) begincase (state)A: next_state = (in) ? A : B;B: next_state = (in) ? B : A;endcaseend// 輸出賦值assign out = (state==B);
endmodule

2.?Fsm1s（Simple FSM 1 - synchronous reset）

注意：由于本題中輸出賦值與狀態值更新處于同一寄存器中，所以變量 present_state 得充當中間變量，使用阻塞賦值語句，否則會其值的更新會落后一個時鐘周期，輸出 out 無法被正確賦值。

????????對于阻塞賦值的中間變量， 使用關鍵字?logic 進行定義。

module top_module(clk, reset, in, out);output 	out; input 	clk;input 	reset;input 	in;reg 	out;parameter A = 0;parameter B = 1;always @(posedge clk) beginlogic present_state;logic next_state;if (reset == 1'b1) begin  present_state	= B;out				<= present_state;end else begin// 狀態值轉換case (present_state)A: next_state = (in) ? A : B;B: next_state = (in) ? B : A;endcase// 狀態值更新present_state = next_state;   // 輸出賦值case (present_state)A: out <= 0;B: out <= 1;endcaseendend
endmodule

3.?Fsm2（Simple FSM 2 - asynchronous reset）

module top_module
#(parameter 	OFF	= 0,parameter 	ON	= 1
)
(output 	out,input 	clk,input 	areset,input 	j,input 	k
); reg state;reg	next_state;// 狀態值更新always @(posedge clk, posedge areset) beginif (areset == 1'b1) beginstate <= OFF;end else beginstate <= next_state;endend// 狀態值轉換always @(*) begincase (state)OFF:	next_state = (j) ? ON : OFF;ON:		next_state = (k) ? OFF : ON;endcaseend// 輸出賦值assign out = (state == ON);
endmodule

4.?Fsm2s（Simple FSM 2 - synchronous reset）

module top_module
#(parameter 	OFF	= 0,parameter	ON	= 1 
)
(output 	out,input 	clk,input 	reset,input 	j,input 	k
);reg state;reg next_state;// 狀態值更新always @(posedge clk) beginif (reset == 1'b1) beginstate <= OFF;end else beginstate <= next_state;endend// 狀態值轉換always @(*) begincase (state)OFF:	next_state = (j) ? ON : OFF;ON:		next_state = (k) ? OFF : ON;endcaseend// 輸出賦值assign out = (state == ON);
endmodule

5.?Fsm3comb（Simple state transitions 3）

module top_module 
#(// 充當數值parameter A = 0, parameter B = 1, parameter C = 2, parameter D = 3
)
(output 			out,output 	[1:0]	next_state,input 			in,input 	[1:0] 	state
);// 狀態值變換always @(*) begincase (state)A: next_state = (in) ? B : A;B: next_state = (in) ? B : C;C: next_state = (in) ? D : A;D: next_state = (in) ? B : C;endcaseend// 輸出賦值assign out = (state == D);
endmodule

6.?Fsm3onehot（Simple one-hot state transitions 3）

module top_module 
#(// 充當序號parameter A = 0, parameter B = 1, parameter C = 2, parameter D = 3
)
(output 			out,output 	[3:0] 	next_state,input 			in,input 	[3:0]	state
);// 輸出賦值assign out = state[3];// 狀態值變換assign next_state[A] = state[0]&(~in)	| state[2]&(~in);assign next_state[B] = state[0]&in 		| state[1]&in 		| state[3]∈assign next_state[C] = state[1]&(~in) 	| state[3]&(~in);assign next_state[D] = state[2]∈
endmodule

7. Fsm3（Simple FSM 3 - asynchronous reset）

module top_module
#(parameter A = 0,parameter B = 1,parameter C = 2,parameter D = 3
)
(output 	reg	out,input 		clk,input 		in,input 		areset
);reg [1:0] sta;reg [1:0] nex_sta;// 狀態值更新always @(posedge clk, posedge areset) beginif (areset == 1'b1) beginsta <= A;end else beginsta <= nex_sta;endend// 狀態值轉換always @(*) begincase (sta)A: nex_sta = (in) ? B : A;B: nex_sta = (in) ? B : C;C: nex_sta = (in) ? D : A;D: nex_sta = (in) ? B : C;endcaseend// 輸出賦值assign out = (sta == D);
endmodule

8.?Fsm3s（Simple FSM 3 - synchronous reset）

module top_module 
#(parameter A = 0,parameter B = 1,parameter C = 2,parameter D = 3
)
(output 	out,input 	clk,input 	in,input 	reset
); reg [1:0] sta;reg [1:0] nex_sta;// 狀態值更新always @(posedge clk) beginif (reset == 1'b1) beginsta <= A;end else beginsta <= nex_sta;endend// 狀態值變換always @(*) begincase (sta)A: nex_sta = (in) ? B : A;B: nex_sta = (in) ? B : C;C: nex_sta = (in) ? D : A;D: nex_sta = (in) ? B : C;endcaseend// 輸出賦值assign out = (sta == D);
endmodule

9.?Exams/ece241 2013 q4（Design a Moore FSM）