目錄

1.簡介

2.主要功能作用

3.MPS控制策略

4.如何更改

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1.簡介

MPS

該參數含義是一個TLP包里攜帶的有效凈荷的最大值是多少字節（該限制條件同時適用于寫操作和讀操作）。

MRRS

該參數含義是一個TLP讀請求包，一次最多能向接收端請求讀出多少字節。（MRRS參數出現的原因大家有沒有想過……其實設定MRRS的原因是為了避免某個設備長時間占用總線）

2.主要功能作用

在MPS在PCIe整體性能中，有至關重要的作用。隨著MPS大小的增加，PCIe傳輸效率也在不斷的提升。不過，在x86的機器中，RC端的MPS通常是128B/256B。在ARM CPU中，為了追求高效性能，部分場景也會設置為512B。

整個PCIe系統中，MPS的大小，跟RC、PCIe Switch、Endpoint都有相互的影響，最終TLP傳輸的數據大小取決與MPS最小的一個設備。比如下圖示例，RC MPS=256B，PCIe Switch MPS=512B，但是EP3 MPS=128B。所以最終數據傳輸的大小采用的是MPS=128B。

以下是一個實例

lspci -s 01:00.0 -vvvv
01:00.0 Non-Volatile memory controller: Toshiba Corporation Device 0116 (prog-if 02 [NVM Express])Subsystem: Toshiba Corporation Device 0001Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-Latency: 0, Cache Line Size: 64 bytesInterrupt: pin A routed to IRQ 16NUMA node: 0Region 0: Memory at 96200000 (64-bit, non-prefetchable) [size=16K]Capabilities: [40] Express (v2) Endpoint, MSI 00DevCap:	MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimitedExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 25.000WDevCtl:	Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset-MaxPayload 256 bytes, MaxReadReq 512 bytesDevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-LnkCap:	Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L0s <2us, L1 <32usClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+LnkCtl:	ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-LnkSta:	Speed 8GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-DevCap2: Completion Timeout: Range AB, TimeoutDis+, LTR+, OBFF Not SupportedDevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF DisabledLnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-Compliance De-emphasis: -6dBLnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-Capabilities: [80] Power Management version 3Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-Capabilities: [90] MSI: Enable- Count=1/32 Maskable+ 64bit+Address: 0000000000000000  Data: 0000Masking: 00000000  Pending: 00000000Capabilities: [b0] MSI-X: Enable+ Count=32 Masked-Vector table: BAR=0 offset=00002000PBA: BAR=0 offset=00003000

3.MPS控制策略

pcie_bus_tune_off   Disable PCIe MPS (Max Payload Size)tuning and use the BIOS-configured MPS defaults.pcie_bus_safe   Set every device's MPS to the largest valuesupported by all devices below the root complex.pcie_bus_perf   Set device MPS to the largest allowable MPSbased on its parent bus. Also set MRRS (Max Read Request Size) to the largest supportedvalue (no larger than the MPS that the deviceor bus can support) for best performance.pcie_bus_peer2peer  Set every device's MPS to 128B, whichevery device is guaranteed to support. This configuration allows peer-to-peer DMA betweenany pair of devices, possibly at the cost ofreduced performance.  This also guaranteesthat hot-added devices will work.

4.如何更改

Linux系統中通過lspci和setpci可以查詢和修改MPS/MRRS參數。

比如：lspci查看設備DevCap寄存器中MPS=512B，最終傳輸用的MPS=256B，MRRS=4KB。

lspci -s 04:00.0 -vvv | grep DevCtl: -C 2

DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited

ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+

DevCtl: Report errors: Correctable- Non-Fatal+ Fatal+ Unsupported-

RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-

MaxPayload 256 bytes, MaxReadReq 4096 bytes
?

如果需要修改MPS或者MRRS，需要先找到Device Control Register中MPS和MRRS的位置，如PCIe Spec定義，MPS在bit5-7，MRRS在bit12-14. 同時Device Control Register的offset是0x8h。