相關閱讀

Synopsyshttps://blog.csdn.net/weixin_45791458/category_12812219.html?spm=1001.2014.3001.5482

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? ? ? ? 在使用report_timing之類的報告命令時，可以使用-significant_digits選項指定報告的精度，在不使用該選項的情況下，命令使用由report_default_significant_digits變量指定的默認精度進行報告。

? ? ? ? 對于不同的工具，該變量的默認值和取值范圍略有差別，如下所示。

Design Compiler：默認值為-1（表示使用命令特定的默認值），取值范圍為-1到13。

IC Compiler：默認值為-1（表示使用命令特定的默認值），取值范圍為-1到13。

PrimeTime：默認值為2，取值范圍為0到13。

PrimePower：默認值為2，取值范圍為0到13。

Fusion Compiler：默認值為2，取值范圍為0到13。

IC Compiler II：默認值為2，取值范圍為0到13。

NanoTime：默認值為3，取值范圍為0到13。

RTL Architect：默認值為2，取值范圍為0到13。

????????并非所有報告命令都支持這個變量，具體需要查看命令手冊。

? ? ? ? 下面展示了report_default_significant_digits變量在PrimeTime中的使用方式。

pt_shell> report_timing
****************************************
Report : timing-path_type full-delay_type max-max_paths 1-sort_by slack
Design : ORCA
Version: O-2018.06-SP1
Date   : Mon Jul 28 18:47:46 2025
****************************************Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg(rising edge-triggered flip-flop clocked by PCI_CLK)Endpoint: pad[1] (output port clocked by PCI_CLK)Path Group: PCI_CLKPath Type: maxMin Clock Paths Derating Factor : 0.90Point                                                   Incr       Path------------------------------------------------------------------------------clock PCI_CLK (rise edge)                               0.00       0.00clock network delay (propagated)                        3.63       3.63I_ORCA_TOP/I_PCI_CORE/pad_en_reg/CP (sdcrq1)            0.00       3.63 rI_ORCA_TOP/I_PCI_CORE/pad_en_reg/Q (sdcrq1)             0.40 &     4.03 rU7/ZN (inv0d1)                                          0.07 &     4.10 fU62/ZN (inv0d1)                                         0.04 &     4.14 rU63/Z (or02d7)                                          0.27 &     4.41 rU63ASTipoInst495/Z (bufbdk)                             0.31 &     4.71 rU63ASTipoInst494/Z (bufbda)                             3.80 &     8.51 rpad_iopad_1/PAD (pc3b03)                                6.12 H    14.63 rpad[1] (inout)                                          0.05      14.68 rdata arrival time                                                 14.68clock PCI_CLK (rise edge)                              15.00      15.00clock network delay (propagated)                        0.00      15.00clock reconvergence pessimism                           0.00      15.00output external delay                                  -4.00      11.00data required time                                                11.00------------------------------------------------------------------------------data required time                                                11.00data arrival time                                                -14.68------------------------------------------------------------------------------slack (VIOLATED)                                                  -3.68pt_shell> set_app_var report_default_significant_digits 4
pt_shell> report_timing
****************************************
Report : timing-path_type full-delay_type max-max_paths 1-sort_by slack
Design : ORCA
Version: O-2018.06-SP1
Date   : Mon Jul 28 18:49:21 2025
****************************************Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg(rising edge-triggered flip-flop clocked by PCI_CLK)Endpoint: pad[1] (output port clocked by PCI_CLK)Path Group: PCI_CLKPath Type: maxMin Clock Paths Derating Factor : 0.9000Point                                                   Incr       Path------------------------------------------------------------------------------clock PCI_CLK (rise edge)                             0.0000     0.0000clock network delay (propagated)                      3.6278     3.6278I_ORCA_TOP/I_PCI_CORE/pad_en_reg/CP (sdcrq1)          0.0000     3.6278 rI_ORCA_TOP/I_PCI_CORE/pad_en_reg/Q (sdcrq1)           0.4038 &   4.0315 rU7/ZN (inv0d1)                                        0.0660 &   4.0976 fU62/ZN (inv0d1)                                       0.0424 &   4.1400 rU63/Z (or02d7)                                        0.2692 &   4.4092 rU63ASTipoInst495/Z (bufbdk)                           0.3057 &   4.7149 rU63ASTipoInst494/Z (bufbda)                           3.7983 &   8.5132 rpad_iopad_1/PAD (pc3b03)                              6.1185 H  14.6317 rpad[1] (inout)                                        0.0484    14.6801 rdata arrival time                                               14.6801clock PCI_CLK (rise edge)                            15.0000    15.0000clock network delay (propagated)                      0.0000    15.0000clock reconvergence pessimism                         0.0000    15.0000output external delay                                -4.0000    11.0000data required time                                              11.0000------------------------------------------------------------------------------data required time                                              11.0000data arrival time                                              -14.6801------------------------------------------------------------------------------slack (VIOLATED)                                                -3.6801pt_shell> report_timing -significant_digits 5
****************************************
Report : timing-path_type full-delay_type max-max_paths 1-sort_by slack
Design : ORCA
Version: O-2018.06-SP1
Date   : Mon Jul 28 18:49:52 2025
****************************************Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_en_reg(rising edge-triggered flip-flop clocked by PCI_CLK)Endpoint: pad[1] (output port clocked by PCI_CLK)Path Group: PCI_CLKPath Type: maxMin Clock Paths Derating Factor : 0.90000Point                                                   Incr       Path------------------------------------------------------------------------------clock PCI_CLK (rise edge)                            0.00000    0.00000clock network delay (propagated)                     3.62777    3.62777I_ORCA_TOP/I_PCI_CORE/pad_en_reg/CP (sdcrq1)         0.00000    3.62777 rI_ORCA_TOP/I_PCI_CORE/pad_en_reg/Q (sdcrq1)          0.40376 &  4.03154 rU7/ZN (inv0d1)                                       0.06603 &  4.09757 fU62/ZN (inv0d1)                                      0.04243 &  4.13999 rU63/Z (or02d7)                                       0.26920 &  4.40919 rU63ASTipoInst495/Z (bufbdk)                          0.30573 &  4.71492 rU63ASTipoInst494/Z (bufbda)                          3.79833 &  8.51324 rpad_iopad_1/PAD (pc3b03)                             6.11847 H 14.63171 rpad[1] (inout)                                       0.04841   14.68012 rdata arrival time                                              14.68012clock PCI_CLK (rise edge)                           15.00000   15.00000clock network delay (propagated)                     0.00000   15.00000clock reconvergence pessimism                        0.00000   15.00000output external delay                               -4.00000   11.00000data required time                                             11.00000------------------------------------------------------------------------------data required time                                             11.00000data arrival time                                              -14.68012------------------------------------------------------------------------------slack (VIOLATED)                                               -3.68012