Overview

首先我們看下 PCIe x協議對 PERST 的要求：

A component must enter the LTSSM Detect state within 20 rms of the end of Fundamental Reset; With a Downstream Port that supports Link speeds greater than5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port.

什么是PERST#

PERST#作為 Fundamental Reset，是直接通過邊帶信號PERST#（PCI Express Reset）產生的。Fundamental Reset 會復位整個PCIe設備，初始化所有與狀態機相關的硬件邏輯，端口狀態以及配置空間中的配置寄存器等（every state machine and all the hardware logic, port states and configuration registers）。但是，也有