1. LED流水燈的FPGA代碼

一個使用狀態機思想來實現LED流水燈的FPGA代碼

這個例子采用VHDL編寫

VHDL代碼示例：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;entity led_flowing isPort ( clk   : in  std_logic;reset : in  std_logic;led   : out std_logic_vector(7 downto 0));
end led_flowing;architecture Behavioral of led_flowing istype state_type is (s0, s1, s2, s3, s4, s5, s6, s7);signal current_state, next_state : state_type;signal count : integer := 0;beginprocess(clk, reset)beginif reset = '1' thencurrent_state <= s0;elsif rising_edge(clk) thencurrent_state <= next_state;end if;end process;process(current_state)begincase current_state iswhen s0 =>led <= "00000001";  -- 燈1亮next_state <= s1;when s1 =>led <= "00000010";  -- 燈2亮next_state <= s2;when s2 =>led <= "00000100";  -- 燈3亮next_state <= s3;when s3 =>led <= "00001000";  -- 燈4亮next_state <= s4;when s4 =>led <= "00010000";  -- 燈5亮next_state <= s5;when s5 =>led <= "00100000";  -- 燈6亮next_state <= s6;when s6 =>led <= "01000000";  -- 燈7亮next_state <= s7;when s7 =>led <= "10000000";  -- 燈8亮next_state <= s0;when others =>led <= "00000000";  -- 關閉所有燈next_state <= s0;end case;end process;end Behavioral;

仿真測試代碼：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;entity tb_led_flowing is
end tb_led_flowing;architecture Behavioral of tb_led_flowing issignal clk   : std_logic := '0';signal reset : std_logic := '0';signal led   : std_logic_vector(7 downto 0);constant CLK_PERIOD : time := 10 ns;beginuut: entity work.led_flowingport map (clk => clk,reset => reset,led => led);-- Clock generationclk_process :processbeginwhile True loopclk <= '0';wait for CLK_PERIOD/2;clk <= '1';wait for CLK_PERIOD/2;end loop;end process;-- Stimulus processstim_proc: processbeginreset <= '1';wait for 20 ns;reset <= '0';wait for 300 ns; -- 放置足夠的時間進行觀察assert false report "End of simulation" severity note;wait;end process;end Behavioral;

流水燈演示：

2. CPLD和FPGA芯片的主要技術區別

CPLD（復雜可編程邏輯器件）與FPGA（現場可編程門陣列）的主要區別：

1、結構與規模：

CPLD：通常具有較小的邏輯單元和較低的延遲，適合簡單的組合邏輯和小規模狀態機。FPGA：具有較大的邏輯塊（邏輯單元），可以支持更復雜的設計和更高的并行處理能力。

2、應用場合：

CPLD：適合用于控制邏輯、狀態機、小型接口或數據處理，通常用于低功耗、高速的應用。244FPGA：適用于需要處理大量并行信號和復雜算法的應用，如圖像處理、數據加速等。