前言
????????XILINX/AMD是大家常用的FPGA，但是在使用其開發工具ISE/Vivado時免不了會遇到很多warning，(大家是不是發現程序越大warning越多？)，并且還有很多warning根據消除不了，看著特心煩？
? ? ? ? 我這里匯總一些我遇到的和記錄的，給大家參考，祝大家都是0warning選手。
列表
warning：HDLCompiler:1499 - "*\RAM_16b_1k.v" Line 39: Empty module remains a black box.
在《Xilinx ISE 5.x 使用詳解》中翻到如下內容：P71?
????書上有云：?
??? “IP核在綜合時一般被認為是黑盒子(Black Box)，綜合器不對黑盒子做任何編譯。將IP核加入工程有兩種方法，一為在工程中新建Coregen IP類型資源，另一種是針對第三方綜合工具而言，同時避免了在新工程中需要重新加入IP核資源的麻煩。也就是將IP核聲明成黑盒子，具體操作時可以利用IP核生成時生成的仿真文件和IP核實例化文件(.veo,.vho)，將仿真文件中的IP核的相關部分原封不動地拷貝到頂層文件中去，聲明IP核模塊，然后將實例化文件內容粘貼到模塊的實例化部分。?
??? 然面，使用Synplify Pro等綜合工具綜合IP核等Xilinx硬件原語時，需要調用相應Xilinx器件的硬件原語聲明文件。位于Synpliy\lib\Xilinx”子目錄中的virtex.v/vhd,virtexe.v/vhd,virtex2.v/vhd,virtex2p.v/vhd等文件就是硬件原語聲明文件。調用時用"include"命令。?
（轉帖）Xilinx CORE Generator心得 - cdy200824的日志 - 電子工程世界-論壇
在生成核開頭的注釋中加上如下注釋
//synthesis attribute box_type "black_box"?
warning：?HDLCompiler:413 - "*\NUC_RAM_INT.v" Line 145: Result of 10-bit expression is truncated to fit in 9-bit target.
計數器的累加值前加上
? cnt 1'b1;
"WARNING:Route:455 - CLK Net:trn_clk_OBUF may have excessive skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template."
Solution
This message informs the user that some loads on the clock net are not clock pins. Therefore, the clock template that is normally used to connect clock pins will not be used to connect the loads. A different routing that involves local routing will be used, potentially inducing some skew on the clock net.
Opening your design in FPGA EDITOR will allow you to see what loads are connected to the clock net, and the cause of the warnings. The amount of skew on the net will be reported in the Place and Route report. If the loads on the net shown in FPGA Editor are in accord with your design, the skew reported in the PAR report is not critical for the design, and the timing constraint requirement on that net is met, then this warning can be safely ignored.
實例原因：在代碼中用到這樣的語句時（ aa’event and aa=’1’）， aa 不是時鐘信號，最多只是時鐘信號產生的一類周期信號， aa 被作為了另一個 進程或模塊的類似周期信號的作用。（我是在行場信號發生器中 出現的這樣的問題，用產生的行同步信號（行同步信號是由全局時鐘信號驅動產生的）再去驅動產生場同步信號，產生的場同步信號相對與輸入的全局時鐘，有一定 的傾斜）
"WARNING:Xst:647 - Input is never used."or"WARNING:Xst:648 - Output is never used."Solution This particular port has been declared in your HDL description, but does not drive or is not driven by any internal logic. Unused input ports will remain in the design, but they will be completely unconnected. If the port is not intended to be used, this message can be safely ignored. To avoid this message, remove any loadless or sourceless elements from your HDL description. Output ports will remain in the final netlist and will be driven by a logic 0. To avoid the message and to save the port resource, remove the unused output port from your HDL description.
實例原因：一般輸入端口不要預留，即使不使用，在代碼中定義的輸入端口就一定要有輸入的；而輸出端口不用到的可以用 OPEN 封上，最常見的是在利用 DLL 和 DCM 時，CLK90，CLK180，CLK270 等一般不用，在端口連接的時候都用 OPEN 封上。
Place:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = BIDIR, DRIVE_STR = 12IO
This may be due to either an insufficient number of sites available on the device, too many prohibited sites,or incompatible I/O Standards locked or range constrained to I/O Banks with valid sites.
This situation could possibly be resolved by one (or all) of the following actions:
a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by using LOC or range constraints.
b) Maximizing available I/O Banks resources for special IOBs by choosing lower capacity I/O Banks if possible.
c) If applicable, decreasing the number of user prohibited sites or using a larger device.
Pack:1654 - The timing-driven placement phase encountered an error.
原因：
Pack:1654 - The timing-driven placement phase encountered an error.
這個錯位是由上一個錯位866引起的。
866是因為頂層文件中輸出信號名mcb1_rzq，但是ddr_mig中rzq的輸出信號寫的是rzq，這就導致rzq的輸出連不上。
Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block .
解決方案：(*KEEP = "TRUE" *)reg [23:0] data_white_ori;
這些寄存器可以設置保留不被優化。
Xst:2677 - Node of sequential type is unconnected in block .
解決辦法：That warning is caused by lot of things.....
One main reason is if your outputs are not connected..ie if you are not reading the module outputs the ise optimisation step removes all signal inside your block and fire a 2677 warning...
check the module outputs。
方法1：把定義多的，用不到的寄存器位寬改成合適大小。
方法2：(*KEEP = "TRUE" *)reg [15:0] ram_rd_data_reg=16'b0; 定義初值，并保持不被優化 有些添加后會出現其他類型的警告
Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
解決：(*KEEP = "TRUE" *)reg [ 7: 0] register_addr=8'b0;給初始值
HDLCompiler:634 - "*\rtl\ddr2_mig_6p.v" Line 365: Net does not have a driver.
線網沒有驅動，那就給加個初值吧。
wire c3_p3_rd_clk=1'b0;
Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND.
信號被用到，但是沒有賦初值，所以默認接到GND
加初值，解決問題 assign rd_franum = 9'd0;
HDLCompiler:189 - "*\poc_framavg.v" Line 298: Size mismatch in connection of port . Formal port size is 9-bit while actual signal size is 16-bit.
給輸入接口的位寬不對，addra定義為9bit，給了10bit，改變輸入數據的位寬為9bit。
ERROR:HDLParsers:3562 - pepExtractor.prj line 1 Expecting 'vhd ' or 'verilog' keyword, found 'work'。 SolutionThis occurs when there are spaces embedded in the project location.
A bad example for project location would be:C:/Documents and Settings/User/example.ise.
A good example fpr project location would be:C:/ISE_tests/example.ise.
實例原因：在 ISE9.1 的版本里，在行為仿真和使用約束編輯器的時候會遇到，主要原因是工程的路徑名里有空格一類的不被要求的非英文字符。
"ERROR:Xst:2587 Port of instance has different
type in definition " .
Solution
Compare the component declaration and instantiation to the submodule that is instantiated. When this error occurs, the declaration matches the instantiation, but does not match the port declarations of the submodule.Change either the port declarations in the declaration/instantiation pair or the submodule port declarations so that they match. This error is specific to the types of ports in the submodule.
實例原因：一般是子模塊宣稱和子模塊的實體定義中端口的寬度和類型(in, out, inout,buffer)不匹配造成的。
XST can generate very large log files for certain designs. In some cases, the generation of these log files can even cause an increase in runtime. How can I eliminate or hide certain frequently generated messages?
Solution
For users of XST via Project Navigator Starting in ISE 7.1i, Project Navigator has the capability to do message filtering for all Xilinx tools. Please refer to the Project Navigator help on how to use this method.
For users of XST via command line You can hide specific messages generated by XST at the HDL or Low-Level Synthesis steps in specific situations by using the XIL_XST_HIDEMESSAGES
environment variable. This environment variable can have one of the following values:
-- none: maximum verbosity. All messages are printed out. This is the default.
-- hdl_level: reduce verbosity during VHDL/Verilog Analysis and HDL Basic and Advanced Synthesis.
-- low_level: reduce verbosity during Low-level Synthesis
-- hdl_and_low_levels: reduce verbosity at all stages
The following messages are hidden when hdl_level or hdl_and_low_levels values are specified for the XIL_XST_HIDEMESSAGES environment variable:
WARNING:HDLCompilers:38 - design.v line xx Macro 'my_macro' redefined
NOTE: This message is issued by the Verilog compiler only.
WARNING:Xst:916 - design.vhd line xx: Delay is ignored for synthesis.
WARNING:Xst:766 - design.vhd line xx: Generating a Black Box for component comp.
Instantiating component comp from Library lib.
Set user-defined property "LOC = X1Y1" for instance inst in unit block.
Set user-defined property "RLOC = X1Y1" for instance inst in unit block.
Set user-defined property "INIT = 1" for instance inst in unit block.
Register reg1 equivalent to reg2 has been removed. The following messages are hidden when low_level or hdl_and_low_levels values are specified for the XIL_XST_HIDEMESSAGES environment variable:
WARNING:Xst:382 - Register reg1 is equivalent to reg2. Register reg1 equivalent to reg2 has been removed.
WARNING:Xst:1710 - FF/Latch reg (without init value) is constant in block block.
WARNING:Xst 1293 - FF/Latch reg is constant in block block.
WARNING:Xst:1291 - FF/Latch reg is unconnected in block block.
WARNING:Xst:1426 - The value init of the FF/Latch reg hinders the constant
cleaning in the block block. You could achieve better results by setting this init to value.
實例原因：在綜合時，有很多的綜合警告是可以忽略的，以上大致的羅列幾項。
"WARNING:Xst:737 - Found n-bit latch for signal ." The listing for "n" is the width of the latch.If latch inference is intended, you can safely ignore this message.However, some inefficient coding styles can lead to accidental latch inference. You should analyze your code to see if this result is intended. The examples below illustrate how you can avoid latch inference.
實例原因：一般出現這樣的問題都是代碼出現了鎖存器，因避免這樣的代碼寫法，電路會不穩定，因利用觸發器去寄存數據在時鐘沿。
Solution 1
Include all possible cases in the case statement
Verilog
always @ (SEL or DIN1 or DIN2)begincase (SEL)2'b00 : DOUT2'b01 : DOUT2'b10 : DOUTendcaseend
VHDL
process (SEL, DIN1, DIN2)begincase SEL iswhen "00" => DOUTwhen "01" => DOUTwhen "10" => DOUTend case;end process;These two examples create latches because there is no provision for the
case when SEL = "11." To eliminate the latches, add another entry to deal
with this possibility.
Verilog
2'b11 : DOUT
VHDL
when "11" => DOUT
Using the "DEFAULT" (Verilog) or "WHEN OTHERS" (VHDL) clause always works,
but this can create extraneous logic. This is always the safest
methodology, but might produce a larger and slower design since any
unknown state has logic that is needed to bring it to a known state.
Solution 2
Assign to all the same outputs in each case.
Verilog
always @ (SEL or DIN1 or DIN2)begincase (SEL)2'b00 : DOUT2'b01 : DOUT2'b10 : DOUT2'b11 :beginDOUTTEMPendendcaseendVHDL
process (SEL, DIN1, DIN2)begincase SEL iswhen "00" => DOUTwhen "01" => DOUTwhen "10" => DOUTwhen "11" =>DOUTTEMPend case;end process;These examples infer latches because the "11" case assigns two outputs,
while the others assign only one. Looking at this case from TEMP's point
of view, only one of four possible cases are specified, so it is
incomplete. You can avoid this situation by assigning values to the exact
same list of outputs for each case.
Solution 3
Make sure any "if / else if" statements have a concluding "else" clause:
VHDL:
process (ge, din)beginif (ge = '1') thendout_aelsedout_a"else" statement.end if;end process;Verilog:
always @(ge or din)if (ge) dout_aelse dout_astatement.在不影響電路功能的情況下，要寫完整的 if--else 語句。（對于時鐘沿觸發時，是不要 else
的)
ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not
placed at an optimal clock IOB / clock site pair. The clock component is
placed at site . The IO component is placed at site
. This will not allow the use of the fast path between the IO and the Clock buffer. If
this sub optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended that this error
condition be corrected in the design. A list of all the COMP.PINs used in this clock
placement rule is listed below. These examples can be used directly in the .ucf file to
override this clock rule. < NET "Ref_Clk_p" CLOCK_DEDICATED_ROUTE = FALSE; >
解決方法： CLK16_inst 和 Ref_Clk 只都用 BUFG，或都用 IBUFG.(個人驗證解決問題，但
不保證一定解決問題)
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
Flash_rst_n is set but the tri state is not configured. Your problem is in the source code,not your constraints. It's complainingthat you don't ever tristate the signal, either because your equations don't have a tristate term or because that term has been optimised away.
就是非輸入加上拉后，沒有配置三態。這是程序的出錯，不關 constraints。
