FPGA學習筆記_李敏兒oc的博客-CSDN博客

TLV5618.v：實現DAC數模轉換，產生模擬信號，輸出指定電壓值

時序圖

FPGA學習筆記：數據采集傳輸系統設計（二）：TLV5618型DAC驅動-CSDN博客

ADC128S052.v：實現ADC模數轉換，將采集到的模擬信號轉換為12位數字信號，實現單次AD采集

FIFO存儲器：調用Quartus II自帶的FIFO IP核，用于存儲連續ADC采樣的數據

FPGA學習筆記：數據采集傳輸系統設計（四）：FIFO IP核調用與仿真波形解讀_fpga dma傳輸來自fifo的數據-CSDN博客

UART串口：包含串口發送和串口接收，用于實現串口通信

ADC_FIFO.v：調用ADC128S052.v，實現連續AD采樣，并將采樣數據存儲至FIFO存儲器

module adc_fifo(input Clk,						//系統時鐘input Rst_n,					//系統復位input Start,					//開始采集標志位output reg AD_Done,				//采集完成標志位input wire ADC_OUT,				//ADC串行數字信號output wire ADC_CS_N,			//ADC片選output wire ADC_DIN,			//串行數據送給ADC芯片output wire ADC_SCLK,			//ADC時鐘output wire ADC_Done,			//單次AD采集完成標志位，仿真時使用input full,						//FIFO滿標志位output reg wrreq,				//FIFO寫使能output reg [11:0] FIFO_DATA		//FIFO數據輸入
);parameter ADC_Cnt_MAX = 11'd128;  //AD采集次數/*****模塊間信號連線*****/	reg ADC_Start;			//單次AD采集開始標志位wire [11:0] ADC_DATA;	//單次AD采集數據/*****本模塊內部寄存器、參數定義*****/	reg ADC_State;			//連續采集狀態reg [10:0] ADC_Cnt;		//采集128次計數器reg [2:0] state;localparam IDLE 			= 3'b001,	//空閑狀態WAIT_ADC_DONE 	= 3'b010,	//等待單次AD采集完成WRITE_FIFO 		= 3'b100;	//延時一拍，數據寫入FIFOalways@(posedge Clk or negedge Rst_n)if(!Rst_n) beginADC_Cnt <= 11'd0;ADC_Start <= 1'b0;wrreq <= 1'b0;FIFO_DATA <= 12'd0;state <= IDLE;endelse begincase(state)IDLE:if(ADC_State) beginADC_Start <= 1'b1;//開啟單次AD采集state <= WAIT_ADC_DONE;endelsestate <= IDLE;WAIT_ADC_DONE:beginADC_Start <= 1'b0;if(ADC_Done == 1'b1) begin//等待AD采集完成FIFO_DATA <= ADC_DATA;wrreq = 1'b1;ADC_Cnt <= ADC_Cnt + 1'b1;state <= WRITE_FIFO;endelsestate <= WAIT_ADC_DONE;endWRITE_FIFO:beginwrreq = 1'b0;if(ADC_Cnt == ADC_Cnt_MAX)ADC_Cnt <= 11'd0;state <= IDLE;enddefault:state <= IDLE;endcaseendalways@(posedge Clk or negedge Rst_n)if(!Rst_n)AD_Done <= 1'b0;else	if(ADC_Cnt == ADC_Cnt_MAX)AD_Done <= 1'b1;else AD_Done <= 1'b0;always@(posedge Clk or negedge Rst_n)if(!Rst_n)ADC_State <= 1'b0;else if(Start)ADC_State <= 1'b1;else if(ADC_Cnt == ADC_Cnt_MAX)ADC_State <= 1'b0;//ADC采集模塊adc128s052 adc1(.Clk(Clk),.Rst_n(Rst_n),.DATA(ADC_DATA),		//并行數字信號.Channel(3'd6),		//通道選擇.Start(ADC_Start),   //開始標志位.Conv_done(ADC_Done),//完成標志位.ADC_CS_N(ADC_CS_N),	//片選.ADC_DIN(ADC_DIN), 	//串行數據送給ADC芯片.ADC_SCLK(ADC_SCLK),	//ADC時鐘.ADC_OUT(ADC_OUT)		//串行數字信號);defparam adc1.DIV_PARAM = 8;//ADC時鐘50/8 = 6.25Mhz
endmodule

FIFO_UART.v：從FIFO中讀取轉換后的數字信號，并將其通過UART發送至PC端

module fifo_uart_tx(input Clk,						//系統時鐘input Rst_n,					//系統復位input Start,					//開始發送數據標志位input empty,					//FIFO空標志位input [11:0] FIFO_Q,			//FIFO數據輸入output reg rdreq,				//FIFO讀使能output reg Uart_done,		//所有數據發送完畢output wire uart_tx 			//串口數據發送端
);parameter UART_Cnt_MAX = 11'd128; //發送數據個數/*****模塊間信號連線*****/	reg send_en;				//單次發送使能reg [7:0] send_data;		//單次發送數據wire tx_done;				//單次發送結束標志/*****本模塊內部寄存器、參數定義*****/		reg [10:0] UART_Cnt;		//發送128次計數器reg [4:0] state;localparamIDLE 				= 5'b00001,		//空閑狀態DELY 				= 5'b00010,		//空一拍延時，等待FIFO_Q數據更新SEND_HIGH 		= 5'b00100,		//發送ADC高四位數據SEND_LOW 		= 5'b01000,		//發送ADC低八位數據WAIT_SEND_DONE = 5'b10000;		//等待發送結束always@(posedge Clk or negedge Rst_n)if(!Rst_n) beginrdreq <= 1'b0;send_en <= 1'b0;send_data <= 8'd0;UART_Cnt <= 11'd0;state <= IDLE;endelse begincase(state)IDLE:if(empty == 1'b1) beginif(UART_Cnt == UART_Cnt_MAX)UART_Cnt <= 11'd0;state <= IDLE;endelse beginrdreq <= 1'b1;state <= DELY;endDELY:begin//空一拍延時，此狀態FIFO_Q數據更新rdreq <= 1'b0;state <= SEND_HIGH;endSEND_HIGH:beginsend_en <= 1'b1;send_data <= {4'd0,FIFO_Q[11:8]};//發送ADC高四位state <= SEND_LOW;endSEND_LOW:beginif(tx_done)begin//等待發送完成send_en <= 1'b1;send_data <= FIFO_Q[7:0];//發送ADC低八位state <= WAIT_SEND_DONE;endelse beginstate <= SEND_LOW;send_en <= 1'b0;endendWAIT_SEND_DONE:beginif(tx_done) begin//等待發送完成UART_Cnt <= UART_Cnt + 1'b1;state <= IDLE;endelse beginstate <= WAIT_SEND_DONE;send_en <= 1'b0;endenddefault:state <= IDLE;	endcaseendalways@(posedge Clk or negedge Rst_n)if(!Rst_n)Uart_done <= 1'b0;else if(UART_Cnt == UART_Cnt_MAX)Uart_done <= 1'b1;elseUart_done <= 1'b0;//串口發送模塊uart_data_tx data_tx(   .Clk(Clk),.Rst_n(Rst_n),.send_en(send_en),.data(send_data),.baud_set(3'd2),		//波特率9600.tx(uart_tx),			//數據發送端.tx_done(tx_done));
endmodule

FPGA學習筆記：數據采集傳輸系統設計（六）：ADC采集FIFO緩存UART發送系統頂層及仿真_fpga adc-CSDN博客