verilog的使用-1

1.判斷上升沿

reg    s_d0;
reg    s_d1;
wire   signal_up ;
//判斷信號的上升沿
assign  signal_up = (~touch_key_d1) & touch_key_d0;
always @ (posedge clk or negedge rst_n) beginif(rst_n == 1'b0) begins_d0<= 1'b0;s_d1<= 1'b0;endelse begins_d0<= signal_in;s_d1<= s_d0;end 
end

2.模塊例化

uart_reveive #(                       //串口接收例化.CLK_FREQ       (CLK_FREQ),       //設置頻率.UART_BPS       (UART_BPS))       //設置波特率
u_uart_receive(                 .sys_clk        (sys_clk), .sys_rst_n      (sys_rst_n),.uart_rxd       (uart_rxd),.uart_done      (uart_w_en),.uart_data      (uart_data_w));

3.時鐘計數

reg [26:0] cnt;
always @(posedge clk or negedge rst_n) beginif (!rst_n)cnt<= 24'd0;else if (cnt< 24'd1000_0000)cnt<= counter + 1'b1;elsecnt<= 26'd0;
end

4.案件消抖

module key_debounce(input            sys_clk,          //外部50M時鐘input            sys_rst_n,        //外部復位信號，低有效input            key_in,              //外部按鍵輸入output reg       key_flag,         //按鍵數據有效信號output reg       key_value         //按鍵消抖后的數據  );reg [31:0] delay_cnt;
reg        key_reg;always @(posedge sys_clk or negedge rst_n) begin if (!rst_n) begin key_reg   <= 1'b1;delay_cnt <= 32'd0;endelse beginkey_reg <= key_in;				//非阻塞賦值，按鍵輸入是wire類型的，隨時可能有值的變化if(key_reg != key_in)          //一旦檢測到按鍵狀態發生變化(有按鍵被按下或釋放)delay_cnt <= 32'd500_000;  //給延時計數器重新裝載初始值（計數時間為10ms）else if(key_reg == key_in) begin  //在按鍵狀態穩定時，計數器遞減，開始10ms倒計時if(delay_cnt > 32'd0)delay_cnt <= delay_cnt - 1'b1;elsedelay_cnt <= delay_cnt;end           end   
end
always @(posedge sys_clk or negedge rst_n) begin if (!rst_n) begin key_flag  <= 1'b0;key_value <= 1'b1;          endelse beginif(delay_cnt == 32'd1) begin   //當計數器遞減到1時，說明按鍵穩定狀態維持了20mskey_flag  <= 1'b1;         //此時消抖過程結束，給出一個時鐘周期的標志信號key_value <= key;          //并寄存此時按鍵的值endelse beginkey_flag  <= 1'b0;key_value <= key_value; end  end   
end

5.時鐘分頻模塊

module clock_generator (input  clk_50m,       		// 50MHz輸入時鐘input  rst_n,         		// 異步低電平復位output reg clk_out,        	// 周期時鐘輸出
);
localparam CNT_CYCLE   = 50_000_000;   //1秒 = 50,000,000個周期
// 計數器定義
reg [26:0] cnt_add;     
// 1秒時鐘生成
always @(posedge clk_50m or negedge rst_n) beginif (!rst_n) begincnt_add <= 0;clk_out <= 0;end else beginif (cnt_add == CNT_CYCLE>>1-1) begincnt_add <= 0;clk_out <= ~clk_out;  // 翻轉產生50%占空比end else begincnt_add <= cnt_add + 1;endend
end