【iCore1S 雙核心板_FPGA】例程十二：基于單口RAM的ARM+FPGA數據存取實驗

實驗現象：

核心代碼：

module single_port_ram(input CLK_12M,input WR,input RD,input CS0,inout [15:0]DB,input [24:16]A,output FPGA_LEDR,output FPGA_LEDG,output FPGA_LEDB);
//----------------------------pll-------------------------------//
    /*實例化MY_PLL模塊，輸出48M時鐘*/my_pll    u1(.inclk0(CLK_12M),.c0(PLL_48M));//---------------------------rst_n----------------------------//                            /*復位信號，10個周期后rst_n置1*/    reg [3:0]cnt_rst=4'd0;
    reg rst_n;always@(posedge CLK_12M)beginif(cnt_rst==4'd10)
                beginrst_n <= 1'd1;cnt_rst <= 4'd10;
                endelse     cnt_rst <= cnt_rst + 1'd1;
        end//-------------------------fsmc-----------------------------//
    wire rd =(CS0|RD);//    提取讀信號wire wr =(CS0|WR);//    提取寫信號
    reg wr_clk1,wr_clk2;always@(posedge PLL_48M or negedge rst_n)beginif(!rst_n)beginwr_clk1 <= 1'd1;wr_clk2 <= 1'd1;
                end else {wr_clk2,wr_clk1} <= {wr_clk1,wr};end wire clk = (!wr_clk2|!rd);  //將讀寫信號轉化為時鐘信號assign DB = !rd?DB_OUT :16'hzzzz;//---------------------------ram-------------------------------//
    /*實例化ram塊*/wire [15:0]DB_OUT;my_ram u2(.address(A),.clock(clk),.data(DB),.wren(!wr),.rden(!rd),.q(DB_OUT));//--------------------------led----------------------------//    
assign FPGA_LEDR = 1'd1;assign FPGA_LEDG = 1'd0;assign FPGA_LEDB = 1'd1;//-----------------------endmodule-------------------------//
endmodule     

實驗方法及指導書:

鏈接：http://pan.baidu.com/s/1jIBXsSu 密碼：38q7