SoC驗證工程師面試常見問題（二）

       摘要：面試SoC驗證工程師時，SystemVerilog (SV) 和 UVM (Universal Verification Methodology) 是核心技能，而AXI總線是現代SoC中最常見的接口協議之一，因此也是必考點。以下是可能被問到的問題及優質答案的詳細列表：

一、 SystemVerilog 相關問題

1.1 基礎與語法

1. Q: SystemVerilog 相對于 Verilog 在驗證方面的主要優勢是什么?

   • A: SystemVerilog offers significant advantages for verification:
     • Object-Oriented Programming (OOP): Enables creating reusable verification components (like drivers, monitors, scoreboards) using classes, inheritance, and polymorphism, which is fundamental for methodologies like UVM.
     • Constrained Randomization: Allows generating complex and diverse stimuli automatically using constraints (constraint), making it easier to hit corner cases.
     • Functional Coverage: Provides mechanisms (covergroup, coverpoint, cross) to measure how well the design functionality has been tested against the verification plan.
     • Assertions (SVA): Offers a concise way to specify design properties and check them dynamically during simulation or statically using formal methods.
     • Enhanced Data Types: Includes richer types like logic, dynamic arrays, associative arrays, queues, structs, unions, enums, which are more powerful and flexible for modeling complex data structures and testbenches.
     • Interfaces: Simplifies connecting modules/components by bundling signals, reducing port connection errors, and allowing definition of behavior (modports, tasks/functions within interfaces).
     • Direct Programming Interface (DPI): Allows easy integration with other languages like C/C++.
     • Concurrency Control: Enhanced mechanisms like fork...join_none, fork...join_any, wait fork, disable fork.

2. Q: Explain the difference between logic, wire, and reg. When would you use logic?

   • A:
     • reg: Can store a value and is typically used in procedural blocks (always, initial). It historically couldn't be driven by continuous assignments or multiple drivers.
     • wire: Represents a physical connection. It cannot store a value (needs continuous driving) and is used for signals assigned via assign statements or connected to module outputs. It can have multiple drivers (requiring resolution logic like wand, wor).
     • logic: Introduced in SystemVerilog, it's a more versatile 4-state data type (0, 1, X, Z). It can be driven by continuous assignments, procedural blocks, or module outputs. It cannot have multiple drivers (unless explicitly specified with a resolution type, which is rare in verification contexts). It's generally recommended to use logic for most signals in SV testbenches and designs unless multiple drivers or specific Verilog compatibility is needed, as it simplifies code and avoids potential reg/wire confusion.

3. Q: What are dynamic arrays, associative arrays, and queues in SystemVerilog? Give use cases.

   • A:
     • Dynamic Arrays: Size is not fixed at compile time and can be changed during runtime using new[] or by assignment. Useful when the number of elements needed isn't known beforehand, like collecting variable-length packets or storing transaction history where the total count isn't predetermined. int dyn_array[]; dyn_array = new[10];
     • Associative Arrays: Act like dictionaries or hash maps, indexed by any data type (not just integers). Useful for sparse data storage or lookups, like mapping addresses to data, storing coverage information indexed by transaction type, or mapping signal names (strings) to their values. int assoc_array[string]; assoc_array["address"] = 32'h1000;
     • Queues: Variable-size, ordered collections (like linked lists) where elements can be added/removed efficiently from the beginning or end (push_back, push_front, pop_back, pop_front). They combine features of dynamic arrays and linked lists. Ideal for modeling FIFOs, collecting transactions in order, or managing lists of available resources. int queue[$]; queue.push_back(5);

4. Q: Explain fork...join, fork...join_any, and fork...join_none.

   • A: These control parallel process execution:
     • fork...join: Parent process waits until all child processes spawned between fork and join complete.
     • fork...join_any: Parent process waits until at least one of the child processes completes. The remaining processes continue running unless explicitly killed.
     • fork...join_none: Parent process continues execution immediately after spawning the child processes. The child processes run in the background concurrently. This is commonly used in testbenches to start drivers, monitors, or checkers that run for the duration of the test.

1.2 OOP & Randomization

1. Q: What is the difference between a class and a struct in SystemVerilog?

   • A:
     • Class: Reference type (uses handles), supports full OOP (inheritance, polymorphism, encapsulation), requires new() constructor to allocate memory, passed by reference. Used extensively in UVM for components and transactions.
     • Struct: Value type, represents a collection of variables grouped together, passed by value (copied on assignment unless ref is used), does not support inheritance directly. Useful for grouping related data, like fields within a packet header.

2. Q: Explain rand and randc. What are constraints?

   • A:
     • rand: Declares a class property as a random variable. When